| Summary: | 碩士 === 國立臺北科技大學 === 電子工程系研究所 === 105 === The thesis proposes a hysteresis-voltage-controlled buck converter using phase-frequency-locked technique and a pulse-width-modulation buck converter using new current-sensing technique.
The first proposed converter is hysteresis-voltage-controlled buck converter using phase-frequency-locked technique. The control loops include an external ramp circuit, a compensator loop, and a phase-frequency-locked loop. To achieve fixed frequency, the phase-locked loop is employed to keep the switching frequency at constant. The circuit is implemented with TSMC 0.18um CMOS process, and the chip area is 1.126 × 1.148 mm2. The input voltage range is 1V to 1.5 V and the output voltage is 0.4 V. When the output current is 50 mA, the circuit has the highest efficiency of 93.28%.
The second proposed converter is a pulse-width-modulation buck converter using new current-sensing technique. This proposed new active current sensing circuit senses the inductor current, and eliminates the sensing current spike when the buck converter switches. The proposed converter does not need a sample and hold circuit. The circuit is implemented with TSMC 0.18um CMOS process, and the chip area is 1.112 × 1.165 mm2. The input voltage range is 1.5V to 1.8V and the output voltage is 1.4V. When the output current is 400 mA, the circuit has the highest efficiency of 94.77%.
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