| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 105 === This thesis proposes a power driver chip which is composed of the power drive circuit and DC-DC buck converter. In the power driver, it includes five BJT transistors, a Schottky diode, a general diode and a high voltage NMOS; and that this circuit is divided into upper and lower arms to control the inductor motor. Those switches of the upper-arm are design not only to establish a charge pump to boost the input voltage level of 58 V but also to drive the power of the control motor. Also, those switches of lower arm boost the input signal level to the supply power. Furthermore, a DC-DC buck converter is considered to supply various bias voltage. The DC-DC buck converter includes: error amplifier, hysteresis comparator, linear ramp generator, non-overlapping circuit, and level shifter circuit. The output signal of the error amplifier is compared with the triangular wave of the linear ramp generator, and the pulse width modulation signal is used to adjust the duty cycle of the power switch stably. Compared with the current-mode pulse width modulation, the adopted voltage-mode PWM reduces the detection current loop and slope compensation with small chip area and small power consumption. All designed circuits are completed with TSMC 0.25μm 1P3M complementary gold-oxygen mixed-signal process. The chip areas of the DC-DC buck converter and the power driver chip are 1.482x1.0 mm2 and 0.982x0.812 mm2, respectively. As the DC-DC buck converter is fed with an input voltage of 15V, the output voltage and current are 5V and 200mA, respectively. Measurements reveal that the maximum output ripple is 3.2mV and the power efficiency is 60% for DC-DC buck converter; and that the power consumption is 6.8W for the power driver.
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