| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 105 === The IEC61000-3-2 Class A current harmonic regulation standard is applied in this thesis to develop a 300W rated output power with digital signal processor as main controlling for three phase boost type rectifier. Different MOSFET switching mode controlling two phase current flow by control strategy is used in this thesis to improve the current distortion and low power factor situation caused by conventional six-pulse rectifier. The concept of the summary to three phase voltage equals to zero indirectly indicates the third phase current flow is controllable. Under the concept mentioned aforementioned, the phase current and the phase voltage on input power source are both cosine wave and be able to reach the same phase which efficiently decreases the harmonic on current as well. The system power factor is improved and the iTHD is reduced by the method mentioned above. The contribution of this thesis are listed as follow:
A. One Voltage Cycle Sampling Interval Method: CPU Timer in digital controller is used to improve conventional ADC sampling interval discriminant method. At first, scan the phase voltage frequency then divide the working interval according to the counter value. The advantage of this method are: (a) Be able to deal with input voltage frequency of bandwidth, (b) Improve the accuracy on interval discriminant, (c) Working function is not influenced when input has lost one phase voltage.
B. 60° Interval Cycle Peak Current Mode Control: With the concept of high current flow to low current flow and consider the polarity of voltage, three-phase boost rectifier are simplified into two sets of signal-phase boost converter in parallel which makes power MOSFET switches on only two arms for each section. Compare to the controlling strategy in the reference, the switching strategy in this thesis is able to reduce 33.3% switching loss.
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