| Summary: | 碩士 === 國立臺北科技大學 === 電機工程研究所 === 105 === This thesis presents a modified direct torque control (DTC), which includes fuzzy PID and seven-stage hysteresis controller, to improve the ripple problem induced with a limited vector voltages and slow response of speed in traditional DTC. To have a stable control system, one needs to increase the response on torque, flux, current and speed. This work proposes a neural network PID for speed response and use a seven-stage hysteresis controller. Both flux and torque errors pass through the modified discrete multiple vector voltages (MDMVV) to obtain the required vector voltage; and the speed error is converted into a torque command after passing the neural PID controller. In this thesis, we use the two-phase current and voltage, and the magnetic flux after calculating the flux estimation to evaluate the actual speed of the motor instead of the encoder. The error of the speed command and the actual value is converted into the torque command value through the neural controller. The magnetic flux and torque are determined by the command value and the estimated value which acts as the fuzzy attribution function.Passing through the MDMVV switch table,one can select a set of vector combinations. There are many advantages of using the estimated speed, which can filter external noise interference, reduce the ripples, and increase the stability of the system.
In this thesis, the hardware description language (HDL) is used to write the source code of the control system; and that the programmable logic gate array (FPGA) device is considered to verify the function and syntax. Next the TSMC (0.18um CMOS) process is adopted to simulate the designed function. By using the component libraries in Synopsys and Cadence software, the source code is completed with circuit synthesis, automatic layout winding and functional testing process. Finally, the direct torque control ASIC is implemented with neural network PID speed controller and sensorless speed. According to the simulated results, the chip area of the proposed DTC ASIC is 1.1761.163 mm2 at the operating frequency of 10 MHz, the supplied voltage of 1.8 V and the power consumption of 6.101 mW.
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