| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 105 === Vernier delay line (VDL) circuits broadly applied to digital circuits, mostly to the measurement circuits of time-to-digital converters and some to the circuits for analog-to-digital converters, jitter measurement, phase-locked loops, and delayed phase-locked loops. However, traditional VDL circuits could not present high resolution and little area at the same time. Although research proposed that VDL circuits with coarse/fine resolution conversion could solve such a problem, the different paths of coarse/fine delay lines could result in measurement errors.
A multi-input logic gate based delay unit is designed a single-path variable time delay circuit in this study. The two electrical delay circuits with time difference are combined to become vernier delay line circuits with picosecond resolution. The input load of the logic gate is changed by a logic state so that the vernier delay line circuits present a coarse/fine resolution to timely expand the measurement range of time difference. Since the coarse/fine delay line path does not require a switch, the circuits could remain the advantages of extremely high time difference resolution and small area. We use this new VDL to measure metastable window of D flip-flop to prove its picosecond time resolution capability. The measurement has three major stages. The first stage of the measurement is for the coarse detection mode, find setup time and hold time windows quickly with a lower resolution. Secondly, detect the setup-time window with high resolution. The third stage measures hold time window with high resolution. The value of the second and third stage measurement results can combine into the size of a metastable window. The circuits are implemented in the CMOS 90nm process with the voltage 1.0V, the delay line level 16, the time resolution up to 1.2ps, and the timing measurement range up to 100ps.
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