A High Resolution Variable Vernier Delay Line Circuit for On-chip Measurement of Metastability
碩士 === 國立雲林科技大學 === 電子工程系 === 105 === Vernier delay line (VDL) circuits broadly applied to digital circuits, mostly to the measurement circuits of time-to-digital converters and some to the circuits for analog-to-digital converters, jitter measurement, phase-locked loops, and delayed phase-locked lo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/rg6b3r |