| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 105 === With the increase of data rate, wiring constraints for digital circuits are more and more stringent. Previous wiring methods may no longer be suitable for today’s high-speed digital circuits. In high-speed digital circuits, serpentine lines have been widely adopted for time-delay and synchronization purposes. Hence, we aim in this thesis to provide guidelines for wiring using serpentine lines in some scenarios, hoping that these guidelines may benefit the industrial development in Taiwan. From time-domain reflectometer signals, we can observe the “macro” characteristic impedance variation along a serpentine line. Various parametric studies were conducted in this thesis to see how the characteristic impedance fluctuates along the line. Using DDR4, PCIe, and SATA as three transmission-interface examples, we further studied how eye diagrams and their associated eye metrics are affected by serpentine lines of various parameters. Sometimes, the physical space is not large enough to allow further adjustment of the serpentine line. One may resort to via-holes or different substrate materials, which may be regarded as cumbersome or impractical in terms of fabrication cost. As a remedy, we proposed three compensation methods to lessen the fluctuation of the characteristic impedance along a serpentine line, without changing the layer stacking and without consuming more circuit layout area.
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