| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 106 === In current very-large-scale-integration design miniature technology, the number of circuits in the same chip size is increasing and the performance is more powerful. To follow the rules of the 22nm process design, global routing and detailed routing are separated into two design steps. However, in the physical design stage, ignoring detailed routing rules during the placement stage may directly lead to design failure. At the same time, to make sure the success of physical design must only after the end of routing stage, so pre-evaluating the routability during the placement stage is a very important issue in the physical design stage.
This paper proposes a novel pre-processing method and a special machine learning model architecture. By extracting more features using pre-processing, we add external conditions that can simplify the relationship of connections between pin and net. Instead of discussing how to grow up the tree, we move the evaluation of congestion to the pre-assessment stage and define it, then push all the feature of our study to machine learning architecture that build from two different model. The model will find out the potential relationship between features and features, and we can build the mechanism for feedback and modify, that can get the best prediction results.
In the future, we will integrate our method into the physical design flow; help the placement stage to avoid the fail in the routing stage.
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