| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 106 === In this thesis, we group the flip-flops to design multiple scan chains. The method of grouping flip-flops requires the arrival data of flip-flops to next flip-flops. By analyzing arrival data and circuit parameters, we establish a mathematical model with 1 target equation and 4 conditional equations, then use the linear programming software “Lingo” to compute the required partitioning results. We can obtain the best or better solutions for partitioning to lower the quantity of violation edges among flip-flop groups. Using the circuit structure of multi-scan chains and Automatic Test Pattern Generation (ATPG) software, we generate the LOC (launch-off-capture) test patterns for transition delay fault (TDF). The ATPG software generate diverse patterns, which can launch and capture between scan chains liberally. These patterns can achieve low power testing of circuit. We check the waveforms of signals to make sure the ATPG software has generated the patterns as we want. Experimental results show that we make most of the circuits reduce the number of violation edges, which increase the fault coverage. In addition, when reducing more violation edges, we obviously improve more fault coverage.
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