Design and Implementation of Slew-Rate Enhancement Circuits

• Main Authors: CHIA-HUNG TAI, 戴嘉宏
• Other Authors: Chun-Chieh Chen
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/m5q6az

碩士 === 中原大學 === 電子工程研究所 === 106 === Nowadays, with the rapid development of science and technology, the application of most electronic circuits is indispensable to life. With the progress of manufacturing processes, the volume is getting smaller and smaller, and the integrated circuits are also designed for fast speed and low power consumption. In order to achieve low power consumption, the use of subthreshold regions (weak reversed regions) has become the current design method. In the case of low voltage, the design must also meet the relevant specifications, such as: DC gain, Gain bandwidth, Phase margin, or Slew rate. This paper uses TSMC 0.18um 1P6M CMOS process to achieve CMOS OTA, to meet a low-power, high slew rate and high-gain multi-stage amplifier operating in the subthreshold region. This paper analyzes the structure and characteristics of folded spliced amplifiers, analyze circuit architecture and bias circuit for simulation and verification. A low-power amplifier is proposed to add a slew-rate enhancement circuit to detect internal node voltages, provide current to the output terminals to achieve faster circuit operation, and almost no extra power consumption is required. Circuit design using 1V power supply. When the load capacitance is 200pF, the simulation result DC gain is 94.38dB. The bandwidth is 10.4kHZ. The power consumption is 255.35nW, and the slew rate is 3.810/-2.5(mV/μs).