Research on DIBL and Punch-through effect of Nanoscale n-type FinFETs

• Main Authors: CHAO, TING-WEI, 趙廷唯
• Other Authors: WANG, MU-CHUN
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/7e3kge

碩士 === 明新科技大學 === 電子工程系碩士班 === 106 === The use of planar transistors has been in the semiconductor industry for some time. With the evolution of the era, business opportunities such as high computational rates, artificial intelligence, virtual reality, 5G communications, automotive electronics and audio and video demand, and Internet of Things have risen rapidly, and ICs have become more and more demanding, with changes in the size of IC chips. Under the premise that the size of the transistor element is a good choice, it is obviously not enough to meet the demand of the above products. In the 16/14 nano process, introducing a three-dimensional structure of fin transistors (FinFETs) to increase the driving current of the transistor is relatively a feasible way to increase the speed of the IC, but the process also faces many challenges. In the FinFET device characteristics, the short-channel effect (SCE) becomes more and more obvious as the size of the device reduced to the nano-scale. The displayed index has a lower energy barrier due to the drain (Drain- Phantom lowering, DIBL) and the punch-through effect of the channel, these two indicators are also the direction balls of the channel control capability, which can detect the quality and integrity of the components. When FinFETs are manufactured to obtain a better starting voltage value (VT), there will be different modulations in the energy value of the ion, but the energy value of the cloth is not unfavorable, but the overall FinFET electrical properties are detrimental, which is also focus on this experiment measurement observation. In this experimental measurement, the gate channel width (W=0.115 μm) of the n-type fin transistor will be matched with different gate channel lengths (L=0.16, 0.24, 0.5, 2, 10 μm). The components were measured for different temperatures (25°C, 50°C, 100°C), VT implant energy (6 KeV and 10 KeV), and Length of source/drain extension (LSDE) with the LSDE=60 nm and 160 nm changes, the DIBL and Punch-through VPT affect the electrical performance of the device. With the discovery of n-type semiconductor devices, the increase in temperature tends to deteriorate the quality of the device, making the already existing DIBL effect more visible and easier to achieve. The DIBL value of 10 KeV implantation energy is slightly larger than the implantation energy of 6 keV DIBL value, while the dose of the fixed VT implantation process, the lower doping energy has good control on the PN junction, so the cloth Plant energy 6 KeV penetration voltage greater than 10 KeV. Compared with LSDE, when the LSDE is large, the effective length increases, the DIBL value decreases, and the device is less likely to penetrate.