A Refined Pulse Generator for High Performance Dual Edge Triggered Flip Flop

• Main Authors: Yi-Jyun Lin, 林依俊
• Other Authors: 張延任
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/a2cruw

碩士 === 國立中興大學 === 資訊科學與工程學系 === 106 === Dual-edge triggered flip-flop is a kind of storage that can perform the write operation at both positive and negative clock edge. Compared to the traditional single-edge triggered flip-flop, because the dual-edge triggered flip-flop has the same performance at half the clock rate, it is widely used to reduce the clock power consumption. In this thesis, we propose a refined pulse generator to improve the performance of dual-edge triggered flip-flop. By reducing the delay between the positive and negative pulse, our design can eliminate the race condition problem that possibly causes the circuit failed. In addition, our design has the strong driver and the symmetrical feature. We use the TSMC 45nm technology process with 1.0V supply voltage to implement the proposed design. Compared to the related work, the HSPICE simulation results show that our design can reduce the pulse rise time and fall time by 65% and 60%, respectively, and reduce the delay between the positive and negative pulse by 48%, such that the performance of dual-edge triggered flip-flop can be improved effectively.