| Summary: | 碩士 === 國立交通大學 === 材料科學與工程學系所 === 106 === Recently, the planar transistors with sub-micro-scale gates have already been the trend of semiconductor industry. Many researches still focus on reducing gate length. However, as the transistor scales down, many problems start appearing, such as VTH roll-off and off-state leakage, or so called short channel effect. Therefore, searching a new channel material and a corresponding fabrication process are urgent to improve the device characteristics.
InAs channel with high electron mobility and low threshold voltage. It matches with InP substrate as well. As a result, we use InAlAs/InAs/InP high electron mobility transistors (HEMTs) to achieve high-speed and low power consumption in this study. Furthermore, by double electron beam lithography and etching, we let the foot of the π-gate directly connect to the bottom InAlAs-buffer layers. Because the gate was connected to both the upper InAlAs and bottom InAlAs-buffer layers and form Shottky contact , the potential energy of the both InAlAs layers was shifted to positive direction when the gate voltage increases. This resulted in the InXGa1-XAs/InAs/InXGa1-XAs layer potential shifts to the positive direction, resulting in the higher electron concentration at the channel. This is the reason for low subthreshold swing (SS) and high ION/IOFF ratio for the π-gate InAs HEMTs.
The results showed that the 3-D π-gate devices present better logic parameter, including lower SS of 62.7 mV/decade, lower off-state leakage current of 0.00935mA/mm and larger ION/IOFF ratio of 3.5 x 104 for low power logic applications(VDS=0.5V).
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