12-bit SAR ADC with Mixed Switching and Background Offset Calibration
碩士 === 國立交通大學 === 電機工程學系 === 106 === This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure...
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ndltd-TW-106NCTU54420192019-05-16T00:08:12Z http://ndltd.ncl.edu.tw/handle/ngq679 12-bit SAR ADC with Mixed Switching and Background Offset Calibration 具混和式切換及背景誤差校正之12位元連續漸進式類比數位轉換器 Hsieh, Yi-Cheng 謝易成 碩士 國立交通大學 電機工程學系 106 This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used. For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step. For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW. Hung, Chung-Chih 洪崇智 2017 學位論文 ; thesis 79 zh-TW |
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碩士 === 國立交通大學 === 電機工程學系 === 106 === This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used.
For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step.
For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW.
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author2 |
Hung, Chung-Chih |
author_facet |
Hung, Chung-Chih Hsieh, Yi-Cheng 謝易成 |
author |
Hsieh, Yi-Cheng 謝易成 |
spellingShingle |
Hsieh, Yi-Cheng 謝易成 12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
author_sort |
Hsieh, Yi-Cheng |
title |
12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
title_short |
12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
title_full |
12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
title_fullStr |
12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
title_full_unstemmed |
12-bit SAR ADC with Mixed Switching and Background Offset Calibration |
title_sort |
12-bit sar adc with mixed switching and background offset calibration |
publishDate |
2017 |
url |
http://ndltd.ncl.edu.tw/handle/ngq679 |
work_keys_str_mv |
AT hsiehyicheng 12bitsaradcwithmixedswitchingandbackgroundoffsetcalibration AT xièyìchéng 12bitsaradcwithmixedswitchingandbackgroundoffsetcalibration AT hsiehyicheng jùhùnhéshìqièhuànjíbèijǐngwùchàxiàozhèngzhī12wèiyuánliánxùjiànjìnshìlèibǐshùwèizhuǎnhuànqì AT xièyìchéng jùhùnhéshìqièhuànjíbèijǐngwùchàxiàozhèngzhī12wèiyuánliánxùjiànjìnshìlèibǐshùwèizhuǎnhuànqì |
_version_ |
1719161797689212928 |