MCFTA: Multi-Corner Functional Timing Analyzer

• Main Authors: Lee, Yue-Cheng, 李岳澄
• Other Authors: Wen, Hung-Pin
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/tq7mda

碩士 === 國立交通大學 === 電機工程學系 === 106 === Timing analysis on multi-corner becomes more important in modern VLSI design flow. In order to achieve a better timing closure, manufacturing process variations which lead to circuit timing variability should be taken into consideration. Multi-corner static timing analysis (MCSTA) was proposed to solve this problem. However, delays calculated by MCSTA are usually too pessimistic, as it evaluates circuit delays without taking false paths into consideration. In this paper, we propose a Multi-Corner timing analysis engine based on functional timing analysis (FTA) which can take false paths in to consideration and compute the worst-case delay more accurate than conventional static timing analysis (STA). However, as the number of process parameters grows, the expanding execution time of FTA becomes a serious issue. Therefore, two techniques: (1) Corner Reordering and Filtering (CRF) and (2) Global Delay Constraint (GDC), are proposed to speed up MCFTA. Experiment results show that the delay values reported by our MCFTA decrease 7% on average and 47% under the best case.