Fast-Locking All-Digital Phase-Locked Loop with Parallel Processing TDC and Interpolated DCO
碩士 === 國立交通大學 === 電機工程學系 === 106 === Phase-locked loops (PLL) generate a stable clock signal as a reference siganl to ensure circuits operate correctly. Nowadays, PLLs are widely used for SOC applications, such as wireless communication synthesizers, so it is indispensable in many applications. The...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5sm43m |