A High Speed Image Preprocessing Hardware Accelerator for Vision Inspection

• Main Authors: Jheng-Lun Ho, 何政倫
• Other Authors: 陳慶瀚
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/x4p2gv

碩士 === 國立中央大學 === 資訊工程學系 === 106 === The machine vision is used in industrial automation production extensively, the inspection environment sometimes influences the imaging quality, so that the subsequent image processing and recognition performance are degraded, and then the overall performance of automatic control system is influenced. This study develops an image preprocessing hardware accelerator for high speed vision inspection systems to improve the imaging quality and performance of machine vision system. We design adaptive image enhancement ADPSHE and adaptive Wellner binarization hardware accelerator. The effect of environment on the inspection efficiency is reduced by two kinds of image preprocessing, the image quality is upgraded, and high speed processing performance is implemented. In order to meet the requirement for different image computing masks, an elastic hardware architecture which can adjust the mask size dynamically is designed, a new image preprocessing hardware accelerator can be obtained by command register setting without changing the circuit. Finally, the image preprocessing hardware accelerator performance is validated by FPGA. On the frequency of 127.81Mhz, this system can process 61 frames with images per second, applicable to real-time, high imaging quality and elastic embedded visual inspection.