| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 106 === Several microwave and millimeter wave (MMW) high linearity track-and-hold amplifiers (THAs) for high speed data conversion systems are presented in this dissertation. Design, investigation and analysis of THAs shown in this dissertation are verified by the experimental results. The introduction and design considerations of THA are demonstrated in Chapter 2 in details.
A compact DC-to-82.4-GHz broadband amplifier using 0.15 μm GaAs E-mode PHEMT process is demonstrated in Chapter 3. The amplifier is implemented in common-source (CS) configuration with bandwidth extension technique. The frequency response and input and output impedances of the amplifier are investigated to obtain the design methodology. The amplifier exhibits a high gain-bandwidth product (GBP) of 328 GHz with a chip size of 0.7 × 1 mm2. Moreover, the amplifier is evaluated using pseudorandom bit stream (PRBS) signal with a data rate up to 40 Gbps. The proposed amplifier has potential for the high-speed data rate transmission due to its superior performance.
A broadband high-speed high-linearity THA is presented in Chapter 4 using 0.18 μm SiGe process. A switched emitter follower (SEF) track-and-hold (T/H) stage with cascode stage is adopted to achieve high resolution for analog-to-digital conversion. A modified Darlington amplifier with peaking technique is used to enhance the input bandwidth. With a DC power consumption of 94.3 mW, the proposed THA demonstrates a 3-dB input bandwidth from DC to 27 GHz, a maximum spurious-free dynamic range (SFDR) of 45 dBc, and a minimum total harmonic distortion (THD) of -43.9 dBc. The proposed circuit has potential for high-speed sampling rate as using time-interleaved architecture due to its superior performance.
Chapter 5 presents the design and analysis of the first GaAs-based THA. The conventional switched source follower (SSF) T/H stage is modified to enhance the sampling rate and resolution. The modified SSF T/H stage is designed and investigated to further reduce input-dependent timing jitter existed in the conventional SSF. Moreover, by using the differential topology, the even mode harmonic distortion is successfully suppressed and the SFDR and THD are improved. With the distributed amplifier (DA)-base input buffer and source follower-based output buffer, the proposed THA features a bandwidth from DC to 16 GHz, a maximum SFDR of 46 dBc and a maximum sampling rate of 13.5 GS/s.
In Chapter 6, a 40 nm CMOS high speed high dynamic range THA is proposed using a differential feed-through cancellation technique. The simulated isolation is approximate to infinity over the input bandwidth as the THA is operated in the hold mode. The linearity and droop rate are enhanced due to the feed-through cancellation. With a sampling rate of 50 GS/s and an input frequency of 5 GHz, the SFDR and THD are better than 47.6 dBc and −44 dBc, respectively. The simulated input bandwidth is up to 60 GHz, and the total DC power consumption is 396 mW. The measured results and resimulated results with several significant layout considerations are detailed as well. The proposed THA can be suitable for the handheld electronic applications, and the circuit performance can be compared to the advanced silicon-based THAs due to its high speed, good linearity, and low DC power.
Lastly, the future work and the conclusions are addressed in Chapter 7.
|
|---|
