| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 106 === This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units.
This all-digital phase-locked loop has the following characteristics:
1. The digitally controlled oscillator uses the low power schmitt trigger inverter as a delay element to reduce power consumption and reduce output jitter.
2. Resolution is divided into 6-bit coarse-tuning and 5-bit fine-tuning , coarse delay time range covers the fine delay time, through the delay component to give the least significant bit resolution
3. The use of improved successive approximation register , can solve the process, voltage and temperature conditions can not continue to track the lock caused by all-digital phase-locked loop deadlock problem, so that the entire phase-locked loop after the lock can continue to do the circuit Locked after tracking.
The supply voltage is 1 V. The reference frequency is 20 MHz. The output frequency can achieve from 250 MHz to 1 GHz. The power consumption is 0.438 mW at 1GHz. The simulation of the jitter is 26.7 ps at 1 GHz.
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