| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 106 === In the communication system, Error Correcting codes (ECC) would become a necessary and important module because it can prevent from the noise disturbance and eliminate the channel response effects. Therefore, it plays a critical role due to meeting the overall system requirement and enhancing data transmission correctness. Among so many kinds of ECC, the one behaving the best error correcting ability in the world is Polar Codes. In the communication theory, its decoding performance is very close to the lower bound, Shannon Limit. As a result, it has been a research spotlight in a rapid progress way. Even more, it will be considered as an indispensable key part in communication and adopted in next-generation 5G applications.
This thesis proposes the Variable-Length FIFO Feedback Architecture. By applying regular and scalable characteristics, the overall encoder architecture can be folded into several stages of modular units. Our proposed radix-2 Polar encoder hardware architecture is composed of some simple XOR gates and variable-length storage units. And then in order to further improve its performance, we propose 32-parallel radix-2 Polar encoder and reconfigurable multi-mode Polar encoder hardware architecture. Our work achieves high-speed and low-area-cost efficient Polar encoder chip, implemented with TSMC 90nm CMOS technology. This low-area-cost, low power dissipation, and high-performance hardware architecture can achieve the requirement of the future wireless communication system and support the future of the rich application of internet of things.
|
|---|
