| Summary: | 碩士 === 國立清華大學 === 電機工程學系所 === 106 === The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC. It combined the redundancy algorithm and the optimization of digital circuit to speed up the conversion. Metal-finger capacitors has smaller capacitance. Then, the area of DAC array can be scaled down and the power consumption can be improved. Application of dynamic logic make ADC become faster. It also make the area smaller then static logic because of less transistors. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhance by channel shunting.
The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1.2V supply voltage. The full rail-to-rail input swing is 1.8V peak to peak. This design achieve signal to noise and distortion ratio of 62.15dB, equivalent to the effective number of bits 10.029.The peak DNL values are -0.01 to +0.01 LSB and the peak INL values are -0.04to +0.04 LSB. The average power consumption is 3.28mW. The area is 90μm×189μm = 0.01701mm2. After digital circuit simplification, the average power consumption becomes 1.851mW and the area becomes 74μm×178μm = 0.01317mm2.
|
|---|
