A 10-Bit 1-GS/s Current-Steering DAC with Improved Dynamic-Performance Techniques

碩士 === 國立清華大學 === 電機工程學系所 === 106 === With the rapid development of communication systems and the need for integration of SoCs, the digital-to-analog converters (DACs) with accurate and massive data transmission have been widely used. Recently, high-speed and high-linearity current-steering digital-...

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Bibliographic Details
Main Authors: Ma, Yu-Qian, 馬有謙
Other Authors: Chu, Ta-Shun
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/5a396j
Description
Summary:碩士 === 國立清華大學 === 電機工程學系所 === 106 === With the rapid development of communication systems and the need for integration of SoCs, the digital-to-analog converters (DACs) with accurate and massive data transmission have been widely used. Recently, high-speed and high-linearity current-steering digital-to-analog converters are widely used architecture. So the trend of the circuit is also going to use a smaller area to achieve a converter with higher speed, high dynamic specification. In order to achieve high specification of SFDR (SpuriousSpurious -Free ree ree ree Dynamic ynamic ynamic ynamic ynamic ynamic Rangeange ange), many non-linear problems need to be solved, such as the mismatch errors among current sources, finite impedance of current sources, high-speed switching transients, etc… The mismatch errors caused by the current source will affect the performance of both static and dynamic. Therefore, this thesis proposes a mechanism of RRHS (Random Rotation-Based Hybrid-Weighted Selector) DEM so that the errors caused by harmonic distortions can be converted more effectively to random white noise which is independent of the input digital code. It can also achieve high-accuracy and high-speed digital-to-analog converters in a smaller area. The use of the Always-on Cascode Stage to reduce the influence of the switching impedance in the finite impedance of the current sources. For high-speed switching transients, the skill of Moderate-Swing which effectively reduces the fluctuation of the current path due to parasitic capacitances is used to switch the switches. In this thesis, a 10-bit current-steering digital-to-analog converter with improved dynamic-performance is implemented. The device is fabricated with TSMC 65 nm and 1P9M complementary MOSFETs. Through the RRHS DEM, Always-on Cascode Stage, Moderate-Swing and other techniques, SFDR can be improved from less than 60dB to at least more than 70dB, also completing a high dynamic specifications of the current-steering digital analog-to-digital converter.