| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === In recent years, with the progress of the process, the low speed problem of subrange successive-approximation register (SAR) ADC has been improved. By virtue of it’s low power consumption characteristics, it has gradually become the mainstream analog-to-digital converter. In low-power SAR ADC design, the quality factor have achieved the femto level. In contrast, the power consumption of power supply circuit had significantly beyond the analog-to-digital converter. In order to ameliorate this problem, this essay propose a hybrid power supply system that is synchronized with the analog-to-digital converter. It can increase the efficiency of the power supply circuit dramatically.
This proposed work can achieve the conversion rate of 400KS/s with 200 KHz input frequency. Including dynamic LDO and SAR ADC, The active area is only 0.0098 mm2. Without external-decoupling capacitor, it consumes 0.334nW and FoMW of 1.63fJ/conversion-step. It is suitable for touch with display driver integration (TDDI) module.
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