Utilization of Relaxation Oscillators in Low-Power Wireless Sensing Applications

博士 === 國立臺灣大學 === 電子工程學研究所 === 106 === As the dramatically increase of the number of sensor nodes in the future wireless sensor network for Internet of things or factory automation, lowering the power consumption of each sensor node becomes an important issue. In this thesis, two essential blocks of...

Full description

Bibliographic Details
Main Authors: Yu-Kai Tsai, 蔡渝楷
Other Authors: Liang-Hung Lu
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/rg3g52
Description
Summary:博士 === 國立臺灣大學 === 電子工程學研究所 === 106 === As the dramatically increase of the number of sensor nodes in the future wireless sensor network for Internet of things or factory automation, lowering the power consumption of each sensor node becomes an important issue. In this thesis, two essential blocks of a typical wireless sensor node are chosen and realized with energy-efficient relaxation oscillators in a 90-nm general-purpose CMOS process. To begin with, a 51.3-MHz CMOS relaxation oscillator is implemented. By pointing out the main challenge of achieving high frequency stability versus temperature is the delay time variation of the comparator, an integrated error feedback (IEF) is proposed to conquer the challenge. Due to the use of the proposed IEF technique and composite resistors, the fabricated circuit demonstrates an average frequency drift of 21.8 ppm/°C for a temperature range from -20 to 100°C. As the supply voltage changes from 0.8 to 1.2 V, the frequency variation is ±0.53%. It is well suited for emerging applications where low-power operations are required. Then, a period-mode oscillator-based capaci-tance-to-digital converter (CDCs) is implemented. With the help of the comprehensive analysis of the noise contribution and the sequential search frequency calibration (SSFC), the CDC achieves an equivalent bits of resolution of 8.8 bit with an FoM of 1.16 pJ/c.-s. for off-chip capacitance ranging from 0 to 15 pF. Furthermore, a frequency-mode oscillator-based capacitance-to-digital converter (CDCs) is implemented for comparison. A linearity compensation method is adopted by considering all causes of nonlinearity in detail. As the result, a highly linear performance can be expected when facing on-chip capacitive sensors or connecting the sensor and the CDC directly by bond wires. The frequency-mode CDC demonstrates an equivalent bits of resolution of 7.9 bit with an FoM of 10.6 pJ/c.-s. for an off-chip capacitance ranging from 0 to 12 pF. Finally, a conclusion of oscillator-based circuits is given.