Design of Voltage-Controlled-Oscillator-Based Continuous-Time Delta-Sigma Analog Front-End Circuit for Low Frequency Sensing Applications

• Main Authors: Han-Chun Chen, 陳翰群
• Other Authors: Tsung-Hsien Lin
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/vqu3cu

碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Sensor systems are becoming more and more important with the progress of IOT and AI. Besides, we hope to integrate whole sensors system which includes sensor interface circuit and digital processor in one chip. Therefore, this thesis focuses on the power and area efficient analog front end (AFE) design. Conventional sensor interface circuit consists of a low noise amplifier and an analog to digital converter (ADC). It is inefficient on both power consumption and area, and also complex to design. To solve the above problem, this thesis uses two voltage control oscillator (VCO) based circuits as the integrator and quantizer to implement the 2nd-order continuous time delta-sigma modulator (CTDSM), merging an ADC with the AFE. This thesis implements and measures the CTDSM in TSMC 180 nm CMOS process. This work uses a VCO and a counter as an integrator. Furthermore, we add another VCO with frequency-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second-stage. The whole loop shows second-order noise shaping. The second-stage quantizes the signal as a digital thermometer code with dynamic element matching (DEM), we do not need the dynamic weighted averaging (DWA). The core area of the chip is 0.19 mm2. This chip using sampling frequency at 1 MHz, with supply voltage of 1.2 V. This chip achieves the signal-to-noise-and-distortion-ratio of 62.5 dB. The power consumption of this chip is 52.4 μW, and the FoMs of the work is 143.7 dB. This chip meets bio-AFE requirement and is outstanding on power consumption and chip area.