A Low-Power High-Channel-Loss Equalizer with CTLE, 3-Tap DFE and SSLMS in 0.11um CMOS process

• Main Authors: Yong-Ren Fang, 方詠仁
• Other Authors: Shen-Iuan Liu
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/8gqa57

碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === The higher image quality and ever-increasing screen size of the display lead to high-speed data rate demand and a long backplane channel. The channel loss is a serious problem and it causes ISI (intersymbol interface) and the raising of BER (bit error rate). Equalizer is used to solve these problems. Besides solving channel loss, the power consumption is an important issue of equalizer in this work. Furthermore, an adaptive algorithm, SSLMS, also be used to calibrate equalizer in this work. This work is divided to two part. First, an adaptive equalizer with two operation mode is proposed to solve 40dB channel loss in 7.5Gbps data rate. The peaking gain of CTLE is decreasing from 20dB to 13.6dB and it reduces 59.3% power consumption of CTLE. Also, SSLMS algorithm and training pattern is used to calibrate equalizer in training mode. After training, the 210-1 PRBS as input with 40dB loss will be well compensate. Second, a reference voltage searching method of SSLMS is proposed. It can provide optimal reference voltage by different amplitude, CM voltage, and PVT variation. This work is fabricated in 0.11-μm CMOS technology with a supply voltage of 1.2V and its active area is 4.84 mm2.