A Low-Power High-Channel-Loss Equalizer with CTLE, 3-Tap DFE and SSLMS in 0.11um CMOS process
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === The higher image quality and ever-increasing screen size of the display lead to high-speed data rate demand and a long backplane channel. The channel loss is a serious problem and it causes ISI (intersymbol interface) and the raising of BER (bit error rate). Eq...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8gqa57 |