Design of PPC Buffer for Diff-RAID/PPC

碩士 === 國立臺灣科技大學 === 資訊工程系 === 106 === NAND flash base solid-state drives(SSDs) has been extensively used in recent years due to its high performance. However, the bit error rate of NAND flash increase when it suffers from enough program and erase cycles. Therefore, Diff-RAID has been adopted to incr...

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Bibliographic Details
Main Authors: Hung-Li Lin, 林紘立
Other Authors: Jen-wei Hsieh
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/ds26ar
Description
Summary:碩士 === 國立臺灣科技大學 === 資訊工程系 === 106 === NAND flash base solid-state drives(SSDs) has been extensively used in recent years due to its high performance. However, the bit error rate of NAND flash increase when it suffers from enough program and erase cycles. Therefore, Diff-RAID has been adopted to increase reliability. It stripes data and generates parity to protect data when it can't correctly read data. Moreover, it allocates the most of the parities to the first SSD called parity SSD. However, parity write is a hot operation. It means parity SSD will age faster than the other SSD in RAID system. In general, RAID system to alleviate this situation by using NVRAM to absorb a lot of parity writes. However, the cost of NVRAM is too high. Therefore, we change the programming mode of parity SSD of Diff-RAID to absorb partial parities with NVRAM. By doing this, we can have the same performance with DIff-RAID that have larger NVRAM. Moreover, we can extend lifetime of parity SSD and the whole RAID system.