A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter
碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Curr...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/g263c6 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Current-Steering DAC is adopted in this thesis to reduce the realization complexity. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough binary-weighted current source array. A newly-proposed current-splitter architecture along with the 2nd to 3rd order gradient cancellation layout is utilized to ensure the required accuracy and ease the circuit design.
The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology powered with 1.2V supply. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be +0.04 ~ -0.03 LSB and +0.07~ -0.02 LSB respectively. With 499.76MHz input sine wave, the spurios free dynamic range (SFDR) is 61 dB. The power consumption is 24 mW and the active area is merely 0.25 mm2.
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