A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter
碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Curr...
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ndltd-TW-106NTUS54281782019-11-28T05:22:09Z http://ndltd.ncl.edu.tw/handle/g263c6 A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter 以改良式分流器實現之高精度十位元二進位電流導向式數位至類比轉換器 Jie-Ru Bai 白潔茹 碩士 國立臺灣科技大學 電子工程系 106 A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Current-Steering DAC is adopted in this thesis to reduce the realization complexity. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough binary-weighted current source array. A newly-proposed current-splitter architecture along with the 2nd to 3rd order gradient cancellation layout is utilized to ensure the required accuracy and ease the circuit design. The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology powered with 1.2V supply. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be +0.04 ~ -0.03 LSB and +0.07~ -0.02 LSB respectively. With 499.76MHz input sine wave, the spurios free dynamic range (SFDR) is 61 dB. The power consumption is 24 mW and the active area is merely 0.25 mm2. Poki Chen 陳伯奇 2018 學位論文 ; thesis 101 zh-TW |
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碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Current-Steering DAC is adopted in this thesis to reduce the realization complexity. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough binary-weighted current source array. A newly-proposed current-splitter architecture along with the 2nd to 3rd order gradient cancellation layout is utilized to ensure the required accuracy and ease the circuit design.
The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology powered with 1.2V supply. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be +0.04 ~ -0.03 LSB and +0.07~ -0.02 LSB respectively. With 499.76MHz input sine wave, the spurios free dynamic range (SFDR) is 61 dB. The power consumption is 24 mW and the active area is merely 0.25 mm2.
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author2 |
Poki Chen |
author_facet |
Poki Chen Jie-Ru Bai 白潔茹 |
author |
Jie-Ru Bai 白潔茹 |
spellingShingle |
Jie-Ru Bai 白潔茹 A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
author_sort |
Jie-Ru Bai |
title |
A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
title_short |
A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
title_full |
A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
title_fullStr |
A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
title_full_unstemmed |
A High Accuracy 10-Bit Binary-Weighted Current-Steering D/A Converter Realized with Enhanced Current Splitter |
title_sort |
high accuracy 10-bit binary-weighted current-steering d/a converter realized with enhanced current splitter |
publishDate |
2018 |
url |
http://ndltd.ncl.edu.tw/handle/g263c6 |
work_keys_str_mv |
AT jierubai ahighaccuracy10bitbinaryweightedcurrentsteeringdaconverterrealizedwithenhancedcurrentsplitter AT báijiérú ahighaccuracy10bitbinaryweightedcurrentsteeringdaconverterrealizedwithenhancedcurrentsplitter AT jierubai yǐgǎiliángshìfēnliúqìshíxiànzhīgāojīngdùshíwèiyuánèrjìnwèidiànliúdǎoxiàngshìshùwèizhìlèibǐzhuǎnhuànqì AT báijiérú yǐgǎiliángshìfēnliúqìshíxiànzhīgāojīngdùshíwèiyuánèrjìnwèidiànliúdǎoxiàngshìshùwèizhìlèibǐzhuǎnhuànqì AT jierubai highaccuracy10bitbinaryweightedcurrentsteeringdaconverterrealizedwithenhancedcurrentsplitter AT báijiérú highaccuracy10bitbinaryweightedcurrentsteeringdaconverterrealizedwithenhancedcurrentsplitter |
_version_ |
1719297926750011392 |