Design of the Ripple Reduction Circuit in Flyback Drivers

碩士 === 國立臺灣科技大學 === 電機工程系 === 106 === In order to achieve the function of high power factor and constant current regulation, most of the light-emitting diode (LED) illumination driver circuits on the market use the flyback converter topology of the critical conduction control mode for circuit design...

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Bibliographic Details
Main Authors: Dong-Han Lee, 李東翰
Other Authors: Ming-Tse Kuo
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/z26n68
Description
Summary:碩士 === 國立臺灣科技大學 === 電機工程系 === 106 === In order to achieve the function of high power factor and constant current regulation, most of the light-emitting diode (LED) illumination driver circuits on the market use the flyback converter topology of the critical conduction control mode for circuit design, but the output direct current (DC) voltage will generate low frequency ripples with twice frequency of the mains frequency. The phenomenon that the load light sources generate flicker frequency, causing the users to have symptoms such as headache, blurred vision, and the like. DC/DC converters are added to filter out low frequency ripples, but it will result in lower overall circuit efficiency, increased volume and cost. This thesis focuses on the development of ripple suppression circuits to replace the traditional two-level architecture. At the beginning of the research, four different forms of ripple suppression circuit architectures are proposed and a single-stage flyback converter is used as the light source driver. The simulation is built by software SIMetrix/SIMPLIS, and the simulation results are analyzed to find the optimal two ripple suppression circuit schemes. Then, the circuit is materialized and combined with the flyback driver for data measurement. Finally, the optimal ripple suppression circuit scheme is proposed by comparing the simulated and measured data. Its best solution has a full load output efficiency of up to 86.19%. Power factor is up to 99.7%. The peak-to-peak value of the output voltage is not only reduced from the original 2.8V to 1.6V, but the efficiency loss caused by the circuit is only about 1%. The power converters are allowed to output a stable and no ripple DC with consuming a small amount of power. This circuit not only has the advantages of high efficiency and high power factor, but also has the characteristics of fast load response.