A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices

碩士 === 國立聯合大學 === 電子工程學系碩士班 === 106 === In today’s world, many electronic products become to be a necessary part of the human life. However, as the application field becomes wider, the operating voltage of electronic components is also increased, too. Especially for the high voltage era, the reliabi...

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Main Authors: LIN, YU-LIN, 林宥霖
Other Authors: CHEN, SHEN-LI
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/29k96f
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description 碩士 === 國立聯合大學 === 電子工程學系碩士班 === 106 === In today’s world, many electronic products become to be a necessary part of the human life. However, as the application field becomes wider, the operating voltage of electronic components is also increased, too. Especially for the high voltage era, the reliability of the device will be very worse and then this situation may be a serious issue of developing product. The reason of components failure is mostly due to a suddent electro static current, therefore how to build an effective ESD protection becomes the important subject of many researches. In this thesis, we are planning to improve the layout of HV nLDMOS DUTs and find out the best ESD reliability structure after detailed investigation. This thesis will be divided into five sections. In section one, the 55nm 32V devices were used, which were the channel length modulation, drain-side STI length modulation, the embbed SCR and discrete modulation in the drain side, and both of source- and drain-side modulations. It can be found that as the channel length and STI width are to be longer, Ron becomes larger and the values of Vt1 and Vh are increased. Here, an LDMOS with a parasitic SCR device will have obviously SCR charactristics especially for the pnp-arranged type. The discrete modulation in the source/drain-side can increase Vt1 and Vh and it can also improve the non-uniform problem, then the It2 of the device will increase obviously. In section two, the 0.25µm 45V components were applied, in whichthe modulation was about an embedded SCR in the drain side. In this part, it can be found that all the structures have low Vt1 and Vh values and show strong SCR characteristics. And, a butted structure can cause the non-uniform problem, so the It2 value will be not good. In section three, 0.25µm 60V devices were used. In order to save the cell layout area, a guardring was added into the device, and then a lot of modulations were carried out on the guardring. According to the experimental data, the ESD protection impact of the modulation in guardring is smaller than the modulation in drain side, it is due to the most of ESD current doesn’t flow through the guardring-modulation structure. Meanwhile, the influence of discrete modulation in the guardring will be investigated. On the other hand, by increasing the length of guardring STI can make the Ron larger, so the Vt1 and Vh will increase, too. Of course, when the guardring STI become too short, the ability of discharge the ESD current will be worse. Next step, as the drain side contacts were removed, the influence of modulation in guardring became very obviously. In section four, 0.25µm 60V devices were used, which was modulation of the horizontal type SCR in the drain side, and it want to find out the affect of the SCR area ratio. After the analysis the experimental data, we found that as the SCR area became larger, the SCR characteristics became more obviously, too. When the SCR area was equal to the LDMOS area, there is the best It2 value being 4.696A. In the last section, some floating polys were inserted between the gate side and the drain side by using 0.25µm 60V devices. This modulation was in order to improve the electric field concentrated problem in the channel and to increase the breakdown voltage. According to the experimental data, as the poly area became larger, the breakdown voltage became higher. Equavalently, the device can endure more higher voltage and the It2 value will be increased, too. On the other hand, the floating poly can cause the depletion area wider, so the Ron value become larger and the Vh value get higher, too. In this thesis process, all the experiments have been done by the actual layout, tape out, and more accurate measurement and verification. Therefore, in the future, I hope that there have some opportunities to propose another better structures and let our electronic components get more wonderful development.
author2 CHEN, SHEN-LI
author_facet CHEN, SHEN-LI
LIN, YU-LIN
林宥霖
author LIN, YU-LIN
林宥霖
spellingShingle LIN, YU-LIN
林宥霖
A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
author_sort LIN, YU-LIN
title A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
title_short A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
title_full A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
title_fullStr A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
title_full_unstemmed A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices
title_sort study of esd-immunity enhancement by layout modulations in hv 32v/45v/60v nldmos devices
publishDate 2018
url http://ndltd.ncl.edu.tw/handle/29k96f
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spelling ndltd-TW-106NUUM04280052019-05-16T00:37:19Z http://ndltd.ncl.edu.tw/handle/29k96f A Study of ESD-Immunity Enhancement by Layout Modulations in HV 32V/45V/60V nLDMOS Devices 高壓32V/45V/60V nLDMOS佈局調變之ESD能力提升研究 LIN, YU-LIN 林宥霖 碩士 國立聯合大學 電子工程學系碩士班 106 In today’s world, many electronic products become to be a necessary part of the human life. However, as the application field becomes wider, the operating voltage of electronic components is also increased, too. Especially for the high voltage era, the reliability of the device will be very worse and then this situation may be a serious issue of developing product. The reason of components failure is mostly due to a suddent electro static current, therefore how to build an effective ESD protection becomes the important subject of many researches. In this thesis, we are planning to improve the layout of HV nLDMOS DUTs and find out the best ESD reliability structure after detailed investigation. This thesis will be divided into five sections. In section one, the 55nm 32V devices were used, which were the channel length modulation, drain-side STI length modulation, the embbed SCR and discrete modulation in the drain side, and both of source- and drain-side modulations. It can be found that as the channel length and STI width are to be longer, Ron becomes larger and the values of Vt1 and Vh are increased. Here, an LDMOS with a parasitic SCR device will have obviously SCR charactristics especially for the pnp-arranged type. The discrete modulation in the source/drain-side can increase Vt1 and Vh and it can also improve the non-uniform problem, then the It2 of the device will increase obviously. In section two, the 0.25µm 45V components were applied, in whichthe modulation was about an embedded SCR in the drain side. In this part, it can be found that all the structures have low Vt1 and Vh values and show strong SCR characteristics. And, a butted structure can cause the non-uniform problem, so the It2 value will be not good. In section three, 0.25µm 60V devices were used. In order to save the cell layout area, a guardring was added into the device, and then a lot of modulations were carried out on the guardring. According to the experimental data, the ESD protection impact of the modulation in guardring is smaller than the modulation in drain side, it is due to the most of ESD current doesn’t flow through the guardring-modulation structure. Meanwhile, the influence of discrete modulation in the guardring will be investigated. On the other hand, by increasing the length of guardring STI can make the Ron larger, so the Vt1 and Vh will increase, too. Of course, when the guardring STI become too short, the ability of discharge the ESD current will be worse. Next step, as the drain side contacts were removed, the influence of modulation in guardring became very obviously. In section four, 0.25µm 60V devices were used, which was modulation of the horizontal type SCR in the drain side, and it want to find out the affect of the SCR area ratio. After the analysis the experimental data, we found that as the SCR area became larger, the SCR characteristics became more obviously, too. When the SCR area was equal to the LDMOS area, there is the best It2 value being 4.696A. In the last section, some floating polys were inserted between the gate side and the drain side by using 0.25µm 60V devices. This modulation was in order to improve the electric field concentrated problem in the channel and to increase the breakdown voltage. According to the experimental data, as the poly area became larger, the breakdown voltage became higher. Equavalently, the device can endure more higher voltage and the It2 value will be increased, too. On the other hand, the floating poly can cause the depletion area wider, so the Ron value become larger and the Vh value get higher, too. In this thesis process, all the experiments have been done by the actual layout, tape out, and more accurate measurement and verification. Therefore, in the future, I hope that there have some opportunities to propose another better structures and let our electronic components get more wonderful development. CHEN, SHEN-LI 陳勝利 2018 學位論文 ; thesis 144 zh-TW