A Study of Shortening Schedule for PCB Layout by Concurrent Design
碩士 === 世新大學 === 資訊管理學研究所(含碩專班) === 106 === The traditional PCB layout can only be handled by one engineer. In order to meet the project schedule, engineers need to work overtime, or apply a rotation system. This kind of work mode will make engineers lose their morale due to long-term overtime work,...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2018
|
Online Access: | http://ndltd.ncl.edu.tw/handle/328ymu |
id |
ndltd-TW-106SHU00396012 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-106SHU003960122019-10-03T03:40:45Z http://ndltd.ncl.edu.tw/handle/328ymu A Study of Shortening Schedule for PCB Layout by Concurrent Design 運用即時同步工程縮短電路佈局設計時程之研究 CHANG, LI-LY 張莉莉 碩士 世新大學 資訊管理學研究所(含碩專班) 106 The traditional PCB layout can only be handled by one engineer. In order to meet the project schedule, engineers need to work overtime, or apply a rotation system. This kind of work mode will make engineers lose their morale due to long-term overtime work, or affect the quality of the project. This study uses Allegro's concurrent design mode, it uses two or more engineers to collaborate on a project, trying to reduce the pressure on the engineers caused by the traditional model, in order to achieve the goal of shortening the project schedule. Through the actual experimental operation, this study summarizes the design methods that can improve the PCB layout schedule and compare the cost. Among them, different electronic products have different conditions that are valued. Not all project schedules are taken into consideration; therefore, all three operating modes have suitable electronic products that can be used. This thesis mainly discusses how to reduce the project duration. Therefore, the mode of the instant synchronous engineering mode 2 is suitable for the primary goal of shortening the PCB layout. WU, WEI-CHEN 吳威震 2018 學位論文 ; thesis 89 zh-TW |
collection |
NDLTD |
language |
zh-TW |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 世新大學 === 資訊管理學研究所(含碩專班) === 106 === The traditional PCB layout can only be handled by one engineer. In order to meet the project schedule, engineers need to work overtime, or apply a rotation system. This kind of work mode will make engineers lose their morale due to long-term overtime work, or affect the quality of the project.
This study uses Allegro's concurrent design mode, it uses two or more engineers to collaborate on a project, trying to reduce the pressure on the engineers caused by the traditional model, in order to achieve the goal of shortening the project schedule. Through the actual experimental operation, this study summarizes the design methods that can improve the PCB layout schedule and compare the cost. Among them, different electronic products have different conditions that are valued. Not all project schedules are taken into consideration; therefore, all three operating modes have suitable electronic products that can be used.
This thesis mainly discusses how to reduce the project duration. Therefore, the mode of the instant synchronous engineering mode 2 is suitable for the primary goal of shortening the PCB layout.
|
author2 |
WU, WEI-CHEN |
author_facet |
WU, WEI-CHEN CHANG, LI-LY 張莉莉 |
author |
CHANG, LI-LY 張莉莉 |
spellingShingle |
CHANG, LI-LY 張莉莉 A Study of Shortening Schedule for PCB Layout by Concurrent Design |
author_sort |
CHANG, LI-LY |
title |
A Study of Shortening Schedule for PCB Layout by Concurrent Design |
title_short |
A Study of Shortening Schedule for PCB Layout by Concurrent Design |
title_full |
A Study of Shortening Schedule for PCB Layout by Concurrent Design |
title_fullStr |
A Study of Shortening Schedule for PCB Layout by Concurrent Design |
title_full_unstemmed |
A Study of Shortening Schedule for PCB Layout by Concurrent Design |
title_sort |
study of shortening schedule for pcb layout by concurrent design |
publishDate |
2018 |
url |
http://ndltd.ncl.edu.tw/handle/328ymu |
work_keys_str_mv |
AT changlily astudyofshorteningscheduleforpcblayoutbyconcurrentdesign AT zhānglìlì astudyofshorteningscheduleforpcblayoutbyconcurrentdesign AT changlily yùnyòngjíshítóngbùgōngchéngsuōduǎndiànlùbùjúshèjìshíchéngzhīyánjiū AT zhānglìlì yùnyòngjíshítóngbùgōngchéngsuōduǎndiànlùbùjúshèjìshíchéngzhīyánjiū AT changlily studyofshorteningscheduleforpcblayoutbyconcurrentdesign AT zhānglìlì studyofshorteningscheduleforpcblayoutbyconcurrentdesign |
_version_ |
1719259238962823168 |