A Reconfigurable Sigma Delta Modulator Analog to Digital Converter with Cyclic Quantize

• Main Authors: HO, YA-LUN, 何亞倫
• Other Authors: LEE, DA-HUEI
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/2nd57w

碩士 === 南臺科技大學 === 電子工程系 === 106 === 　　With the rapid development of medical electronics, autotronics, and wearable devices as the result of advances of Internet of Things (IoT), a great quantity of sensors have been used to collect natural signals, later transformed into digital signals for data analysis. Such process leads to inventions of analog-to-digital converters (ADC) of diverse specifications. For example, in measuring the temperature, temperature changes are slow yet such measurement requires precision, with ADC featuring low velocity and high resolution needed for data transformation. In monitoring rhythms of the heart, the wave pattern of heartbeats is fast and the need for precision is relatively lower, thus ADC featuring moderate velocity and moderate resolution is used for data transformation. Therefore, designing an ADC featuring low cost, low consumption, and wide coverage was the focus of this study. 　　This study proposed a specification-resettable sigma-delta ADC featuring the combination of cyclic ADC and sigma-delta ADC. While the former used digital counters to switch the output bits and resolution, the latter could adjust the oversampling ratio to satisfy the band signals in different conditions. The combination of two types of ADC turned the proposed converter into a bit-frequency-adjustable ADC. Compared with changing the series-parallel connections or the addition of elements in some sigma-delta ADCs, the proposed ADC in this study could effectively reduce the chip measure, increase transformation efficiency, and most importantly, satisfy operations in different environments, thus reducing the time to develop ADCs with different specifications. 　　The development of the proposed specification-resettable sigma-delta ADC was based on the TSMC’s 0.18um 1P6M 3.3V_CMOS process. With 3-bit quantizer, 64 times oversampling ratio, 6.144 MHz sampling frequency, sound signal between 20 Hz and 20 KHz, the signal-to-noise ratio could reach 107 dB and the consumption was 100mW. The results of the study showed the innovative ADC’s capacity to fit changes in oversampling ratio and output bits, thus capable of replacing most of the ADCs featuring high resolution and low velocity. Keywords: Sigma-Delta ADC, Cyclic ADC, Specification-Resettable Sigma-Delta ADC, Oversampling Ratio, Noise Shaping