Design of a 90nm BCD Integrated High Voltage NMOS and HCI Degradation Dependence on Device Design Parameters

• Main Author: SHAIK MASTANBASHEER
• Other Authors: GENE SHEU
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/2757dh

碩士 === 亞洲大學 === 資訊工程學系 === 106 === In recent years one of the most interesting trend is the emergence of specialized process technologies, especially the Bipolar-CMOS-DMOS (BCD) process technology, which is typically used to make products where high power or voltage ideally needs to be controlled by a digital controller BCD technology incorporates analog components (Bipolar), digital components (CMOS) and high-voltage transistors (DMOS) on the same die. In this work we have developed a high voltage NMOS with the asymmetry and symmetry structures to integrate with the advanced 90nm BCD process. In the BCD process the main constrain is the process conditions, because process conditions are not optimizable for each device. So, we have developed device optimizing technique with the fixed process conditions by using the synopses TCAD simulation tools. We have successfully developed a 20V asymmetric and symmetric NMOS and from this optimization technique and we can go up to 40V with the fixed process conditions. We have developed both asymmetric and symmetric device and symmetry device has the advantage of interchangeable source and drain, this is very suitable to design layout with interchangeable terminals. Hot Carrier Injection (HCI) is a phenomenon in solid-state electronic devices where an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. In this study we have examine how device design parameters can affect degradation due to the hot carrier injection in high voltage NMOS devices with symmetry and asymmetry layouts. We have simulated the Hot Carrier Injection by using the thermodynamic simulation models. According to reliability models, a short-channel MOS transistor is susceptible to the device characteristics degradation due to the hot carrier injection (HCI) effect. In this study, we describe an anomalous degradation behaviour that is opposite to the general understandings on the high-voltage NMOS transistor. We explored causes to this unusual degradation and device optimization techniques to improve the HCI degradation.