Design of Fast-Locking SAR-based Delay-Locked Loop

• Main Authors: Huang, Jia-Jin, 黃家晉
• Other Authors: Hwang, Chorng-Sii
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/r5pt3r

碩士 === 國立雲林科技大學 === 電機工程系 === 106 === Nowadays electronic products can effectively improve the convenience of most people. And the chips are one kind of the key components. For the demand of the instant video and voice, the fast data transfer rate is an indispensable specification. Therefore, the operating clock frequency of the chips is getting higher and higher. If the clock phases of the internal block circuits cannot be synchronized, the circuit function will not be performed correctly. Delay-locked loop (DLL) can be used to solve the aforementioned clock synchronization problem. All-digital delay-locked loop (ADDLL) has the advantages of low power, small area, fast locking, ... etc., and is widely used in the system-on-a-chip (SoC). The successive approximation register-controlled delay-locking loop (SARDLL) adopts the binary search algorithm, which determines the most significant bit to the least significant bit. Consequently, the number of lock cycles is proportional to the bit number of the digital control delay line. In this thesis, the conventional SARDLL is improved with only a single digital-controlled delay line. In the coarse delay line, the dual-bit acquisition method can effectively reduce the number of locking cycles. The proposed chip verification uses the TSMC CMOS 0.18 μm 1P6M process for design and simulation. The operating voltage is 1.8 V. The 10-bit digital-controlled delay line is adopted to achieve a resolution of 12.98 ps. The range of the operating frequency is within 71.4 ~ 830 MHz. The lock period is 14 reference clock cycles, and the maximum power consumption is 14.2 mW.