Analysis and Design of Near-Threshold Dynamic Circuits for Low-Energy Designs

• Main Authors: FANG, YA-BEI, 方雅蓓
• Other Authors: WANG, JINN-SHYAN
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/ynz6kb

碩士 === 國立中正大學 === 電機工程研究所 === 107 === For lowly duty-cycled applications, i.e., IoT edge devices, require low active power and low leakage power to achieve low-energy consumption. NP-RCA [11] has already outperformed the static circuit in energy consumption aspect. Based on [11], this work proposes All-N-RCA, which uses the cost-effective feedback control keeper, power transistor splicing design and RBB technology in PMOS to achieve high speed and low leakage characteristics. Compare to the SRCA and NP-RCA, All-N-RCA is 21% and 12% faster respectively. The active power consumption has 5% and 38% reduction, and leakage power consumption has 82% and 73% reduction with voltage scaling technique. CORDIC [11] replaces the SRCA with All-N-RCA to verify the benefits of dynamic circuits. This work analyzes the D1-1_CORDIC and proposed an optimization methodology based on the concept of D2-1_CORDIC[11] and eventually implemented in the D2-2_CORDIC circuit. In addition, three circuits comparison results are obtained with a different circuit evaluation method compare to [11] : (1) S-1_CORDIC, (2) D1-2_CORDIC, and (3) D2-2_CORDIC. All the designs are based on 28nm CMOS technology node. For an IoT application with 0.02% duty cycle, the All-N-RCA, D1-2_CORDIC and D2-2_CORDIC achieve 57%, 24%, and 20% energy reduction compare to the static counterpart at the typical process corner, respectively.