Hardware Design Optimization and FPGA Implementation of an Optical Remote Sensing Image Compression System

• Main Authors: Zheng-Jie Li, 李政杰
• Other Authors: Yin-Tsung Hwang
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22107NCHU5441084%22.&searchmode=basic

碩士 === 國立中興大學 === 電機工程學系所 === 107 === For the task of optical telemetry imaging on satellites, Convention on Space Data System (CCSDS) has developed a new standard for data compression. Reducing the amount of data through image data compression can not only reduce the amount of data storage space, but also reduce the transmission bandwidth, so that satellites and ground receiving station can achieve real-time synchronous transmission. The compression standard is a variation of JPEG2000 and SPIHT, and specializes in optical remote sensing applications. The algorithm can be divided into two major parts: Discrete Wavelet Transform(DWT) and Bit-Plane Encoder(BPE). The purpose of DWT is to remove the correlation between data, and BPE is to compress and encode the sub-band coefficients generated by the DWT decomposition of the input image. It also provides compression ratio and image quality adjustment mechanism. A third-order discrete wavelet transform is first applied to the input image. DWT can be a lossless integer type or a lossy floating type. Integer type DWT adopts a lifting wavelet transform, and the floating type DWT employs a 9/7 filter architecture. The ten sub-bands generated by the DWT are classified into DC coefficients and AC coefficients. BPE will perform compression and encoding operations, respectively on each class of coefficients. Because the BPE module indicates a bottleneck in design, a design balance must be maintained between the throughput and hardware complexity. In this thesis, an efficient hardware architecture dedidcated to the image data compression system is developed. In the BPE part, because the DWT coefficients are scanned and compressed in a bit-plane by bit-plane manner, the amount of data to be processed increases significantly. In order to keep up with the throughput of the DWT module, a parallel processing hardware architecture is developed. By reorganizing the DWT coefficients into a bit-plane-wise access format, 16 sets of scan and mapping hardware are used to simultaneously process 16 blocks of data to achieve the required computing parallelism. In this thesis, we design a complete hardware circuit architecture subject to the CCSDS 122.0-B-1 standard specifications. It can support 5120 X 2560 sized input image, and employ extensive pipeline and parallel technologies for hardware acceleration and parallel processing, in memory usage optimization, we combined our BRAMs to reduce our memory usage and optimize our circuit design by changing the EDA Tool''s implementation strategy. The maximum operating frequency of the proposed hardware design can reach 126.36MHz in FPGA implementation. This is equivalent to processing more than 23,040 lines per second when the width of input image is under 5120 pixels per line. The CCSDS encoder design is verified based on the concept of hardware/software co-verification. After the image data compression performed by the hardware, the generated bit-stream file is processed by a software decoder through the matlab GUI interface to restore the image. The experimental results indicate the average PSNR value of the 6 test images provided by CCSDS is 50 dB when the compression ratio is 8.