| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 107 === In this work, we realize single photon avalanche diode(SPAD) by using EPISIL 0.8μm CMOS technology. In addition, we implement two SPADs device by using standard CMOS technology which is P+/NWELL SPAD, N+/PWELL SPAD and PWELL/NBL SPAD. Particularly, P+/NWELL SPAD with 27.8V breakdown voltage has a better performance with 10% excess, for example, low dark count rate(DCR) is 56Hz, high photon detect probability(PDP) is 15.38%@495nm, timing jitter FWHM is 157ps. To improve N+/PWELL SPAD and PWELL/NBL SPAD’s characteristics, we introduce the customized CMOS technology for new SPAD(SPAD-A, SPAD-B). From TCAD simulation result, SPAD-A’s breakdown voltage is identical but the depletion width is wider compared with P+/NWELL. The other way, SPAD-B’s breakdown voltage is decreased by using retrograded well. In the end, the customized SPAD’s characteristics are abnormal, whose breakdown voltage is not excepted by simulation. We found out the problem which is the simulation model for ion implant and doping diffuse is not accurate. Although the experiment is not work successfully, it provide the appropriate design flow for future research.
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