Convolution-Neural-Network Model for Predicting DRC Violations of Detailed Routing Based on Global Route Report
碩士 === 國立交通大學 === 電子研究所 === 107 === Due to the progress of manufacture, the routability of a circuit is hard to predict. There is less correlation between global routing congestion report and design rule constrain(DRC) violation location after detailed routing which may lead to a failed layout. This...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/f85c76 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 107 === Due to the progress of manufacture, the routability of a circuit is hard to predict. There is less correlation between global routing congestion report and design rule constrain(DRC) violation location after detailed routing which may lead to a failed layout. This thesis proposed a DRC violation prediction based on convolution neural network. Our features are extracted from global routing congestion report. The experiments are conducted based on 3 floorplanning types of 16 industrial designs. We use class-weighted loss function to handle imbalanced data. We also propose a method which can effectively reduce the training samples leading to a significant reduction of training time. Based on convolution neural network, our prediction is more accurate than global routing congestion report, and can also show the level of the number of DRC violations.
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