An All-Digital Phase-Locked Loop with Dual-Mode Low-Power TDC

碩士 === 國立交通大學 === 電機工程學系 === 107 === Nowadays, the phase-locked loop (PLL) is widely used in many applications of SOC, such as wireless communication ICs, clock recovery, microprocessor, and interface between chips. The analog PLL, or charge-pump PLL (CPPLL) has been developing for many years, and i...

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Bibliographic Details
Main Authors: Wu, Bo-You, 吳柏佑
Other Authors: Hung, Chung-Chih
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/2c2th8

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