| Summary: | 博士 === 國立交通大學 === 電機工程學系 === 107 === Shared-memory systems enable parallel computing for Automatic Test Pattern
Generation (ATPG). Although existing parallel ATPG can reach near-linear speedup,
the problem of test inflation becomes a critical issue to its practicality. This thesis consisting
of a deterministic ATPG and a non-deterministic ATPG focuses on minimizing
test inflation and accelerating runtime. For deterministic perspective, a deterministic
parallel test pattern generation (TPG) engine was realized and generated the same test
pattern set as the serial ATPG does during acceleration. However, for retaining the
determinism, tremendous idle time is observed when different tasks were synchronized
among threads. Therefore, a new parallel TPG engine called P4-TPG is developed and
incorporates preemptive, proactive and preventive schedulings to further save/reuse the
idle time during acceleration. Experimental results show that P4-TPG not only generates
the same test pattern set as the serial TPG does but also achieves averagely
10.36X speedups using 12 threads on 17 benchmark circuits. For non-deterministic
perspective, since the speedup of a deterministic parallel TPG is limited by determinism,
a multi-thread test pattern generation called MT-TPG is proposed to suppress
test inflation and accelerate fault processing, simultaneously, to achiever higher parallelism.
According to our experimental results, MT-TPG can successfully suppress
test inflation to < 4% on 17 benchmark circuits and achieve 13.7X speedup using 16
threads on average. As a result, MT-TPG is proven effective at unleashing parallelism
with minimal test inflation on shared-memory systems.
|
|---|
