| Summary: | 碩士 === 國立中央大學 === 通訊工程學系 === 107 === Our laboratory use Realistic Software-defined Radio platform to implement Digital Video Broadcasting Terrestrial(DVB-T) receiver. We combine FPGA and Radio Frequency module(AD9361) to finish SDR platform. In this thesis, we design baseband receiver for demodulation and Decoder DVB-T signal. This baseband receiver needs the digital signal processing units which are down sampling, time synchronizer, frequency synchronizer, Fast Fourier Transform processor, channel estimator, channel equalizer, symbol de-interleaver, soft decision, bit de-interleaver, Viterbi decoder, packet synchronizer, outer de-interleaver, Reed Solomon decoder, de-scrambler. The signal which is under demodulation and decoder is MPEG-2 Transport Stream, and we can play the video via VLC player.
First, we record DVB-T signal on Matlab and demodulate the signal. Furthermore, we design baseband digital signal processing units by using Verilog hardware description language and verify with iSim. Then, the real-time hardware is implemented and verified with SDR platform. After it is under demodulation and decoder, we are able to get MPEG-2 Transport Stream. We could play this Transport Stream to verify baseband receiver’s result.
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