| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 107 === This thesis proposes a low power, high linearity and rail-to-rail voltage to frequency converter (VFC) employed in wireless sensor networks (WSN).
To achieve low power consumption and rail-to-rail operation, I propose the VFC, utilizing a two-stage voltage division method to attenuate the input signal voltage. In the first stage, the input voltage divider consists of six MOSFETs operated at sub-threshold region. An output voltage equals to one third of the input voltage was obtained from the divider. In the second stage, I adopt the feed-forward voltage attenuation (FFVA) method to divide the voltage further. Based on these two methods, the VFC possess lower power consumption and the voltage-to-current converter (V-I converter) obtains a current output which has a linear relation to the input voltage in rail-to-rail range.
The proposed VFC circuit has been simulated in TSMC 0.18 μm CMOS technology. When the VFC operated at 1.8 V, the simulation results shown that at input voltage range from 0 V to 1.8 V, the VFC produces a corresponding output frequency from 87 kHz to 1.87 MHz. The maximum deviation between theoretical and simulated results is less then 3.5%. The sensitivity of the circuit is approximate 0.99 MHz/V and the maximum power consumption at the input voltage 1.8 V is 172 μW.
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