High Efficiency Buck Converter with Wide Load Current Range Using Dual-mode of PWM and PSM and A 12-bit 100 MS/s Current Steering DAC Using Dynamic Element Matching and Return to Zero Techniques

碩士 === 國立中山大學 === 電機工程學系研究所 === 107 === The Implementation of Signal Processing Chips”. Particularly, these topics applied the photonic gyro system are high-efficiency buck converter with wide load current range using dual-mode of PWM and PSM and 12-bit 100 MS/s current steering DAC using dynamic el...

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Bibliographic Details
Main Authors: Chia-Hsin Hsu, 徐嘉欣
Other Authors: Chua-Chin Wang
Format: Others
Language:zh-TW
Published: 2019
Online Access:http://ndltd.ncl.edu.tw/handle/d652de
Description
Summary:碩士 === 國立中山大學 === 電機工程學系研究所 === 107 === The Implementation of Signal Processing Chips”. Particularly, these topics applied the photonic gyro system are high-efficiency buck converter with wide load current range using dual-mode of PWM and PSM and 12-bit 100 MS/s current steering DAC using dynamic element matching and return to zero techniques. They are implemented using TSMC 0.35 um Mixed-Signal 2P4M Polycide 3.3/5 V and TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5 V processes, respectively. The proposed high efficiency buck converter is featured with integration of PWM and PSM modes to increase the efficiency given a wide load current range. The peak efficiency is 96.76 % when the load current is 1000 mA, while the efficiency in the load current range from 10 mA to 1000 mA is over 94.80 %. In addition, the proposed design accurately switches between heavy load current and light load current by a well-designed logic decoder circuit. A dynamic element matching and return to zero techniques are used to realize a 12- bit 100 MS/s current steering DAC with a precision of 1 to 10◦/h for the Heterogeneous Silicon Photonics Gyroscope. A pseudo-random number generator carries out the random selection of current sources to reduce the mismatch among these current sources caused by layout issues and also reduce the delay by using compact return to zero technique. Not only is the circuit area greatly reduced, the SFDR is also enhanced to 61 dB at 100 MS/s.