| Summary: | 碩士 === 國立臺灣師範大學 === 電機工程學系 === 107 === The first circuit is a 38 GHz two stage power amplifier utilize transmission line matching network to achieve output matching and input impedance. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, the power amplifier exhibits the power gain of 15.63 dB, the saturated output power of 20.31 dBm, the output power of 18.9 dBm at 1-dB compression point, the quiescent current of approximately 81.5 mA and the maximum power added efficiency of approximately 23.8%. The chip size is 1.2 mm × 0.8 mm.
The second circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.2 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.61 dB, the input and output reflection coefficient (S11, S22) of -7.81 dB and -13.23 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.12 dBm. The chip size is 1.2 mm × 0.8 mm.
The third circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source cascade resistance configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.3 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.43 dB, the input and output reflection coefficient (S11, S22) of -9.23 dB and -11.81 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 13.55 dBm. The chip size is 1.2 mm × 0.8 mm.
The fourth circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using cascode configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.4 V), the power amplifier exhibits the small signal gain (S21) of approximately 11.56 dB, the input and output reflection coefficient (S11, S22) of -9.28 dB and -12.3 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.42 dBm. The chip size is 1.2 mm × 0.8 mm.
The fifth circuit is a 38 GHz power amplifier with transformer power combining technique. To achieve input impedance matching, output power matching, we utilize the transformer to implement the impedance conversion and the power combining. At 38 GHz and the VG1 of the power amplifier operate in 0.6 V, the power amplifier exhibits the power gain of 15.07 dB, the saturated output power of 19.98 dBm, the output power of 15.05 dBm at 1-dB compression point, the quiescent current of approximately 114 mA and the maximum power added efficiency of approximately 29.42 %. The chip size is 0.47 mm × 0.57 mm.
The last circuit is a 24 GHz power amplifier with transformer power combining technique and current combining technique. To achieve high output power, we utilize the current combining technique. At 24 GHz and the VG1 of the power amplifier operate in 1 V, the power amplifier exhibits the power gain of 18.07 dB, the saturated output power of 23.9 dBm, the output power of 19.07 dBm at 1-dB compression point, the quiescent current of approximately 354.06 mA and the maximum power added efficiency of approximately 13.63 %. The chip size is 0.99 mm × 0.91 mm.
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