| Summary: | 碩士 === 國立臺灣師範大學 === 電機工程學系 === 107 === In recent years, with the development of high-speed communication between the Internet of Things and the fifth-generation mobile communication, data transmission requires a wider bandwidth to meet a large number of data transmission, transmission frequency must move to a higher frequency to obtain high frequency bandwidth requirements. Therefore, the problem of high frequency signal intrinsic path loss becomes a problem that must be overcome. This paper studies the phase shifter design of millimeter wave phase array system, using beamforming. Technology to solve the problem of excessive loss of high frequency transmission path.
Chapter3 introduces the ka-band five-bit switching phase shifter. The circuit is implemented by standard 0.18-μm 1P6M complementary metal oxide semiconductor process (Standard 0.18-μm 1P6M CMOS process), in which four bits adopt T-bridge. The phase shifter architecture uses another high-low-pass network architecture. The circuit power consumption is 0mW, the overall chip area is 0.84 mm2, the operating frequency is 26GHz to 31GHz, the input reflection coefficient is less than -7.1dB, the output reflection coefficient is less than -5.2dB, the RMS phase error is less than 5.37°, and the RMS amplitude error is less than 0.85dB
Chapter4 improve the problem of poor phase shift bandwidth in Chapter 3, the 90° phase shifter adopts Reflection Type Pahse Shifter (RTPS) and the 180° phase shifter uses phase Invertible Variable Attenuator(PIVA), the remaining bits are all T-bridge architecture. The operating frequency is 26 to 31 GHz, the circuit power consumption is 0 mW, the overall wafer area is 0.64 mm2, the input reflection coefficient is less than -13.1 dB, the output reflection coefficient is less than -5.5 dB, the RMS phase error is less than 3.07 °, and the RMS amplitude error is less than 1.06 dB.
Chapter5 introduces the ka-band five-bit switching phase shifter. The circuit is implemented by standard 65-nm 1P9M complementary metal oxide semiconductor process (Standard 65-nm 1P9M CMOS process), in order to reduce the load effect between phase shifters. The 180° phase shifter is composed of two 90° T bridge phase shifters, so that the five-bit phase shifter adopts the T-bridge phase shifter architecture. The circuit power consumption is 0 mW, the overall chip area is 0.39mm2, the operating frequency is 36GHz to 40GHz, the input reflection coefficient is less than -8.8dB, the output reflection coefficient is less than -8.2dB, the RMS phase error is less than 7.3°, and the RMS amplitude error is less than 1.8 dB.
Chapter6 introduces the Ka-band vector synthesis phase shifter. The circuit is implemented by the standard 65-nm 1P9M complementary metal oxide semiconductor process (Standard 65-nm 1P9M CMOS process), the phase shift resolution is 5Bit, and the control circuit is adjustable. With a resolution of 6Bit, this architecture provides an adjustable continuous phase. In practice, a 6Bit Digital Analog Converter (DAC) must be integrated. The circuit power consumption is 6.6mW, the overall chip area is 0.37mm2, the input reflection coefficient is less than -19.6dB, the output reflection coefficient is less than -5.5dB, the RMS vibration error is 0.17dB, and the RMS phase error is 1.67°
|
|---|
