A Study of Crystallization on Dipped Substrate Wafer Technology for Crystalline Silicon Solar Cells

碩士 === 國立臺灣大學 === 化學工程學研究所 === 107 === With the shortage of fossil energy and global warming, the urgency of using renewal energy has driven the growth of photovoltaic (PV) industry very rapidly. The global annual installation has been grown over 100 times since 2000 and the annual installation in 2...

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Bibliographic Details
Main Authors: Han-Lin Yang, 楊翰霖
Other Authors: Chung-Wen Lan
Format: Others
Language:zh-TW
Published: 2019
Online Access:http://ndltd.ncl.edu.tw/handle/4x94vu
Description
Summary:碩士 === 國立臺灣大學 === 化學工程學研究所 === 107 === With the shortage of fossil energy and global warming, the urgency of using renewal energy has driven the growth of photovoltaic (PV) industry very rapidly. The global annual installation has been grown over 100 times since 2000 and the annual installation in 2014 was expected to be over 40 GWp. With this rapid development, the silicon solar cell still remains the main stream in the market, and its production cost is lower than 33 cents/Wp. Nevertheless, the silicon wafer is still the major cost. More importantly, the slicing (about 10 cents/Wp) is much more costly than ingot growth, and the silicon kerf loss is over 40 %. Therefore, to further reduce the wafer cost, the development of kerf-free wafer technology is necessary. In fact, the kerf-free technology, such as dip casting, is not new. However, the wafer quality is still not good enough to compete with that from ingot growth due to the defect formation during crystal growth. In this research, we designed Si3N4 plates as a substrate, so that the wettability of the silicon melt could be controlled. An in-situ infrared rapid thermal furnace will be used to observe the effect of pressure and substrate on the shape of molten silicon on different substrate, so the thickness of the grown silicon can be controlled. Also, the wafer grain structures, such as the grain structure, grain size, grain orientation, and grain boundary evolution, will be investigated. The distribution of the thermal stress and dislocation, as well as the minority carrier lifetime can be measured. We will also modify and improve the process to achieve a better wafer quality by understanding the effect of the substratea temperature, casting speed, and cooling time.