Design of CMOS Sensor Interface Circuits for EEG and Hall Sensor Applications
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === In this dissertation, two circuits are presented. The first one realizes a low-power and low-noise analog front-end circuit for EEG application. It is fabricated in UMC 180-nm process. The analog front-end (AFE) includes a low-noise instrumentation amplifier (L...
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| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/x3a5qh |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === In this dissertation, two circuits are presented. The first one realizes a low-power and low-noise analog front-end circuit for EEG application. It is fabricated in UMC 180-nm process. The analog front-end (AFE) includes a low-noise instrumentation amplifier (LNA) followed by a programmable gain amplifier (PGA) to further increase the gain. Both LNA and PGA employ capacitively-coupled IA (CCIA) topology to achieve good power efficiency. This chip uses the architecture without chopper technique and achieves total power consumption 3.24 uW per channel. The integrated noise from 0.5 to 400 Hz is 1.7 uVrms. The noise efficiency factor (NEF) is 3.7.
The second work implements an area-efficient voltage-controlled oscillator (VCO) based ADC for a Hall sensor system. It is fabricated in TSMC 180-nm process. A sensor interface circuit that consists of a transducer and a read-out circuit is realized. In the read-out circuit, we merge the IA together with ADC in order to achieve good area efficiency. Also, chopper technique / spinning current technique is added to suppress the flicker noise. This work proposes a digital chopper that solves the residual offset from CCO mismatches, and digital offset reduction loop (DORL) that deals with the dynamic range issue of the ADC. The core area of the circuit is 0.25 mm2. The SNR is 50 dB (with the bandwidth of 2.5 kHz) under 150 mT input magnetic field signal. The figure of merits (FoM) FoMs equals to 121 dB and FoMw is 147 pJ/conv.
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