| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === The digital low dropout voltage regulator(DLDO) gets significant attention due to its low voltage operation capability and process scalability. Usually, a synchronous control mechanism w ill be adopted in conventional DLDO designs. With synchronous control, the shift register could only turn on or off one power transistor in one single clock cycle. The transient response will be limited by operating frequency. With the operating frequency increased, the quiescent current consumption will also be increased.
A 200 MHz digital low dropout regulator with dynamic voltage scaling for power management is proposed in this paper. The design uses a synchronous control method to reduce quiescent current consumption and boost the operating frequency without sacrificing transient response, allowing the DLDO to achieve for dynamic voltage scaling Measurements using a 180nm CMOS prototy pe chip show a load current is switched 490mA, an input voltage rang e of 1.2V to 2V, and an output voltage range of 1.15V to 1.95V. With a voltage regulation up to steady state, the minimum quiescent current can be reduced to 2.55uA. Besides , the proposed D LDO achieves a load regulation of 0.06 mV / mA.
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